1. Field of the Invention
The present invention relates to a clock control device, a clock control method, a clock control program and an integrated circuit for controlling the switching of a clock signal supplied to a central processing unit in the event of a memory stall.
2. Description of the Background Art
In recent years, computer systems provided with processors, cache devices and external input/output ports have become more functional by including a plurality of processors, a plurality of external input/output ports and a plurality of buses having different operation clocks and widths and integration on one chip has been developed. In computer systems, circuitries have become more complicated, for example, by the presence of a memory controller for mediating bus accesses competing among a plurality of processors. There has been a striking improvement in operation clocks of central processing units (hereinafter, called “CPUs”). Further, operation clocks of CPUs of computer systems for controlling portable electronic devices operable, for example, on batteries such as PDAs (Personal Data Assistants), mobile communication terminals, digital cameras and portable audio devices have been and are being steadily improved. On the other hand, there is also a high demand for not only the speeding-up of CPUs, but also lower power consumption for portable electronic devices.
In order to reduce the power consumption of such a computer system, clock gating technology is introduced to processors and busses of the computer system in some cases. The clock gating technology is for reducing the power consumption of the entire computer system by stopping the supply of a clock signal to a circuit block for a period corresponding to an arbitrary number of cycles if an unused circuit block is temporarily present.
In computer systems of recent years, operation clocks of CPUs have been remarkably extended but, in comparison with that, extension rates of operation clocks of buses connected with the CPUs and external main storage devices are low. Thus, upon access to a memory, a phenomenon called a memory stall, in which a CPU is caused to wait, occurs. At this time, a clock signal continues to be supplied since the CPU needs to resume its operation upon completing the memory access. Therefore, even with the introduction of the clock gating technology, a power saving effect is low and a current of several tens of milliamperes flows in some cases.
As conventional technology for reducing power consumption in the event of a memory stall, there has been the one for generating as many clock supply stop signals as clocks corresponding to a set weight number and stopping a clock signal to be supplied at least to one of a CPU and a cache device in a programmable weight controller used for access to an external memory in the event of a cache miss (see, for example, patent literature 1).
However, in the conventional construction, even if an instruction following an instruction issued in the event of a memory stall is executable regardless of an order, it cannot be executed since the clock signal to be supplied to the CPU is stopped. Thus, there has been a problem of causing reduced performance.
[Patent Literature 1]
    Japanese Unexamined Patent Publication No. 2002-6979